Memory cell with reduced parasitic capacitance and method of manufacturing the same
US-2024334680-A1 · Oct 3, 2024 · US
Non-volatile memory device
US9000511B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9000511-B2 |
| Application number | US-201213529621-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 21, 2012 |
| Priority date | Jun 21, 2011 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.
First claim
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What is claimed is: 1. A non-volatile memory device comprising: a substrate having an active region defined by a device isolation region, the device isolation region having a trench and an air gap, a sidewall of the trench being straight from a top to a bottom of the trench such that a width of the trench decreases with increasing depth; a device isolation pattern positioned at a lower portion of the trench such that the air gap is positioned at an upper portion of the trench co…
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- What does patent US9000511B2 cover?
- A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which…
- Who is the assignee on this patent?
- Chang Sung-Il, Park Young-Woo, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W10/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).