Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
US8999863B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999863-B2 |
| Application number | US-13337508-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 5, 2008 |
| Priority date | Jun 5, 2008 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an IC comprising: providing a substrate having first and second active regions defined thereon, the first active region comprises a first transistor of a first type and the second active region comprises a second transistor of a second type; forming a continuous first stress liner on the substrate covering the first and second transistors, wherein the continuous first stress liner comprises a first stress; forming a mask to protec…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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