Stress liner for stress engineering

US8999863B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8999863-B2
Application numberUS-13337508-A
CountryUS
Kind codeB2
Filing dateJun 5, 2008
Priority dateJun 5, 2008
Publication dateApr 7, 2015
Grant dateApr 7, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating an IC comprising: providing a substrate having first and second active regions defined thereon, the first active region comprises a first transistor of a first type and the second active region comprises a second transistor of a second type; forming a continuous first stress liner on the substrate covering the first and second transistors, wherein the continuous first stress liner comprises a first stress; forming a mask to protec…

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What does patent US8999863B2 cover?
A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
Who is the assignee on this patent?
Lee Jae Gon, Tian Jingze, Tan Shyue Seng, and 4 more
What technology area does this patent fall under?
Primary CPC classification H10D84/0167. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).