Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Semiconductor device and fabricating method thereof
US8999843B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999843-B2 |
| Application number | US-201313927830-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 26, 2013 |
| Priority date | Sep 24, 2012 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device and method of fabricating the device are provided, the method including providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming connection holes to the active region in the insulating layer to expose at least part of the active region, wherein the connection holes include a first portion of a first width and a second portion of a second width, the first portion of the connection holes being adjacent to the active region, and the first width being less than the second width; filling the connection holes with a metal material to form the contacts to the active region. As such, contacts formed for the active region also include a first portion of a first width and a second portion of a second width.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a semiconductor device, comprising: providing an insulating layer on the semiconductor device, wherein the insulating layer covers an active region and a gate on the semiconductor device; forming at least one connection hole in the insulating layer, wherein the at least one connection hole includes a first portion having a first width and a second portion having a second width, wherein the first portion of the connection hole is adj…
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Classifications
Electricity · mapped topic
- H10W20/089Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8999843B2 cover?
- A semiconductor device and method of fabricating the device are provided, the method including providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming connection holes to the active region in the insulating layer to expose at least part of the active region, wherein the connection holes include a first portion …
- Who is the assignee on this patent?
- Semiconductor Mfg Int Corp, Semiconductor Mfg Int Shanghai
- What technology area does this patent fall under?
- Primary CPC classification H10W20/089. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).