Method and structure of monolithically integrated ESD supperssion device

Patent metadata

Field	Value
Publication number	US-8999835-B2
Application number	US-201213410273-A
Country	US
Kind code	B2
Filing date	Mar 1, 2012
Priority date	Jul 28, 2008
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.

First claim

What is claimed is:

1. A method for fabricating an electrostatic discharge device for an integrated circuit, the method comprising:
providing a semiconductor substrate;
forming a voltage discharge region overlying an inner portion of the semiconductor substrate, the forming of the voltage discharged region comprising:
forming a plurality of isolated conductive regions arranged as a vertical array, the array being numbered from 1 through N in a first direction and the array bei…

Assignees

• Yang Xiao Charles
• Mcube Inc

Inventors

• Yang Xiao Charles

Classifications

• H10W72/90

  Electricity · mapped topic

• H10W42/60

  Electricity · mapped topic

• H10D89/60 Primary

  Electricity · mapped topic

• H01L23/60

  Electricity · mapped topic

• H01L27/0248 Primary

  Electricity · mapped topic