Method for manufacturing semiconductor device by performing multiple ion implantation processes

Patent metadata

Field	Value
Publication number	US-8999824-B2
Application number	US-201414302103-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 25, 2013
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n + impurity layer on the whole back surface of n − semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n + cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p + impurity layer in the interior of the n + impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p + the n + impurity layers activated.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device comprising the steps of:
performing a first ion implanting process for implanting an n-type impurity with a first dose on a surface of a semiconductor wafer to form an n-type impurity layer on the surface of the semiconductor wafer;
coating resist on the surface of the side where the n-type impurity layer is formed in the semiconductor wafer;
exposing the semiconductor wafer selectively to pattern the res…

Assignees

• Fuji Electric Co Ltd

Inventors

• Noguchi Seiji
• Kuribayashi Hidenao

Classifications

• H10P95/90

  Electricity · mapped topic

• H10P52/00

  Electricity · mapped topic

• H10P50/71

  Electricity · mapped topic

• H10P32/1406 Primary

  Electricity · mapped topic

• H10P32/171

  Electricity · mapped topic