Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Semiconductor device and method of manufacturing semiconductor device
US8999818B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999818-B2 |
| Application number | US-34215308-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2008 |
| Priority date | Dec 28, 2007 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor element including a transistor including a gate electrode and a semiconductor film on a first surface of a glass substrate; thinning the substrate from a second surface side opposite to the first surface to form a thinned substrate having a third surface opposite to the first surface; forming a first groove on the third surface side and in the thinned substrate; form…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8999818B2 cover?
- A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of th…
- Who is the assignee on this patent?
- Takahashi Hidekazu, Yamada Daiki, Monma Yohei, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D86/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).