P-fet with graded silicon-germanium channel
US-2015364555-A1 · Dec 17, 2015 · US
Graphene devices and methods of manufacturing the same
US8999812B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999812-B2 |
| Application number | US-201213475098-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 18, 2012 |
| Priority date | Dec 23, 2011 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a graphene device, the method comprising: forming at least one stacked structure on a first substrate, the at least one stacked structure including a sacrificial layer, a catalyst layer, and a graphene layer sequentially stacked thereon; adhering a second substrate onto the at least one stacked structure; and separating the first substrate by etching the sacrificial layer; wherein the etching comprises one of dry etching and w…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/6741Primary
Electricity · mapped topic
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- What does patent US8999812B2 cover?
- A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating l…
- Who is the assignee on this patent?
- Xianyu Wenxu, Moon Chang-Youl, Lee Jeong-Yub, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6741. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).