Nanowire channel field effect device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-8999801-B2
Application number	US-201113236199-A
Country	US
Kind code	B2
Filing date	Sep 19, 2011
Priority date	Mar 18, 2011
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a first insulating film on a semiconductor substrate;
forming a first semiconductor layer on the first insulating film, and forming a mask on an upper face of the first semiconductor layer, the first semiconductor layer including:
a first region having:
a first side face and a second side face opposite to the first side face, and
a first width along a first direction from the first side face to the second side face;

a second region having a second width along a second direction parallel to the first direction, the second width being greater than the first width; and
a third region having a third width along a third direction parallel to the first direction, the third width being greater than the first width,
at least one of the second and third regions being connected to the first region, and
the first, second, and third regions being covered by the mask;

performing, using the mask, a first ion implantation to implant ions into substantially the entire first region through the first and second side faces of the first region of the first semiconductor layer to transform the first region to an amorphous semiconductor;
performing, after the first ion implantation is performed, a first heat treatment including:
crystallizing the first region of the first semiconductor layer, with crystals in the at least one of the second and third regions being seed crystals;

forming, after the mask is removed, a gate insulating film at least on the first and second side faces of the first region of the first semiconductor layer;
forming a gate electrode on the gate insulating film;
forming gate sidewalls made of an insulating material on side faces of the gate electrode on sides of the second and third regions; and
performing a second ion implantation at least into the second and third regions of the first semiconductor layer.

2. The method according to claim 1 , wherein
the first semiconductor layer prior to the first ion implantation is a polycrystalline semiconductor layer.

3. The method according to claim 1 , wherein the performing of the first ion implantation includes implanting ions in a direction tilted with respect to a direction from the second region to the third region and at an angle that is greater than 0 degree but is smaller than 90 degrees with respect to a normal line of an upper face of the first region.

4. The method according to claim 1 , wherein
the first semiconductor layer is an amorphous semiconductor layer before the mask is formed, and
the method further comprises polycrystallizing the first semiconductor layer by performing a second heat treatment, after the mask is formed and before the first ion implantation is performed.

5. The method according to claim 1 , wherein
the first semiconductor layer is an amorphous semiconductor layer before the mask is formed,
the forming of the first semiconductor layer and the mask on the upper face of the first semiconductor layer includes:
forming the amorphous semiconductor layer on the first insulating film;
forming a mask layer on the amorphous semiconductor layer;
forming a mask by performing patterning on the mask layer; and
performing patterning on the first semiconductor layer, using the mask, and

the method further comprises polycrystallizing the first semiconductor layer by performing a second heat treatment, after the mask is formed and before the first ion implantation is performed.

6. The method according to claim 1 , wherein the first region of the first semiconductor layer is connected to the second and third regions.

7. The method according to claim 1 , wherein an ion species used in the performing the first ion implantation is one of Ge, F, N, C, B, P, As, Ar, and Si.

Assignees

• Ota Kensuke
• Saitoh Masumi
• Numata Toshinori
• Toshiba Kk

Inventors

• Ota Kensuke
• Saitoh Masumi
• Numata Toshinori

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title