Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Method of reducing contact resistance
US8999800B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999800-B2 |
| Application number | US-201313921678-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 19, 2013 |
| Priority date | Dec 12, 2012 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming low contact resistance in a substrate, comprising forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region; and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., the hot implant effective to generate an activated dopant layer containing the dopant species, the activated…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10P30/204Primary
Electricity · mapped topic
- H10P30/21Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8999800B2 cover?
- In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effec…
- Who is the assignee on this patent?
- Varian Semiconductor Equipment
- What technology area does this patent fall under?
- Primary CPC classification H10P30/204. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).