Semiconductor structure with reduced leakage current and method for manufacturing the same
US-2024413223-A1 · Dec 12, 2024 · US
Maskless dual silicide contact formation
US8999799B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999799-B2 |
| Application number | US-201314013110-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 29, 2013 |
| Priority date | Aug 29, 2013 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a top portion of the second set of epitaxial source/drain regions into a metal silicide and the sacrificial epitaxial layer into a sacrificial silicide layer in a silicidation process wherein the first set of epitaxial source/drain regions underneath the sacrificial epitaxial layer is not affected by the silicidation process; removing selectively the sacrificial silicide layer; and converting a top portion of the first set of epitaxial source/drain regions into another metal silicide.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of said first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; and converting at least a top portion of said second set of epitaxial source/drain regions into a metal silicide and said sacrificial epitaxial layer into a sacrific…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8999799B2 cover?
- Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a …
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D84/017. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).