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Integration of high voltage trench transistor with low voltage CMOS transistor
US8999769B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999769-B2 |
| Application number | US-201213552607-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 18, 2012 |
| Priority date | Jul 18, 2012 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a device comprising: providing a substrate defined with a device region, wherein the device region comprises a first polarity type first doped well; forming a gate having an upper and a lower portion in a trench in the substrate, wherein the upper portion forms a gate electrode and the lower portion forms a gate field plate; forming second and third doped wells disposed within the first doped well, wherein the second doped well compr…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8999769B2 cover?
- A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces ver…
- Who is the assignee on this patent?
- Verma Purakh Raj, Yi Liang, Dong Yemin, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0179. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).