Interconnect layer and method for manufacturing the same
US-2024420994-A1 · Dec 19, 2024 · US
US8999764B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999764-B2 |
| Application number | US-83681907-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 10, 2007 |
| Priority date | Aug 10, 2007 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Official abstract text for this publication.
Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
Opening claim text (preview).
What is claimed is: 1. A method comprising: forming a first layer of an integrated circuit (IC) chip, the first layer including at least one of a transistor, resistor, capacitor or interconnecting wire; forming a first metallization layer over the first layer; forming at least one dielectric layer over the first metallization layer, the at least one dielectric layer including ionizing radiation blocking material therein, wherein the ionizing radiation blocking material is conf…
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