Methods and system for analysis and management of parametric yield

Patent metadata

Field	Value
Publication number	US-8997028-B2
Application number	US-201313867621-A
Country	US
Kind code	B2
Filing date	Apr 22, 2013
Priority date	Oct 23, 2007
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

First claim

What is claimed is:

1. A method of identifying a location of anomalous functionality on a semiconductor chip, said method comprising:
by a computer:
determining at least one of spatial distribution of on-current within said semiconductor chip and spatial distribution of off-current within said semiconductor chip;
converting one of said spatial distribution of on-current and said spatial distribution of said off-current into an estimated spatial temperature distribution map; and…

Assignees

• Mentor Graphics Corp

Inventors

• Culp James A
• Chang Paul
• Chidambarrao Dureseti
• Elakkumanan Praveen
• Hibbeler Jason
• Mocuta Anda C

Classifications

• G01R31/26 Primary

  Physics · mapped topic

• G06F30/30 Primary

  Physics · mapped topic

• G06F17/5045

  Physics · mapped topic