Low-density parity-check decoder

US8996972B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-8996972-B1
Application numberUS-201414179179-A
CountryUS
Kind codeB1
Filing dateFeb 12, 2014
Priority dateFeb 11, 2011
Publication dateMar 31, 2015
Grant dateMar 31, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

This disclosure describes a low-density parity-check (LDPC) decoder that is configured to decode a codeword using an iterative process. The decoder includes a first syndrome memory configured to store a syndrome result determined in a previous iteration. The decoder further includes circuitry to flip bits of the codeword based on the syndrome result and one or more parity-check equations, and a second syndrome memory configured to update a current syndrome result during a current iteration based on the bits of the codeword that are flipped by the circuitry.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of decoding a codeword using a low-density parity-check (LDPC) decoder, the method comprising: storing the codeword in a memory; storing, in a first syndrome memory, a syndrome result of the codeword determined in a previous iteration; flipping bits of the codeword based on the syndrome result and one or more parity-check equations; and updating a current syndrome result in a second syndrome memory during a current iteration based on the bits…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8996972B1 cover?
This disclosure describes a low-density parity-check (LDPC) decoder that is configured to decode a codeword using an iterative process. The decoder includes a first syndrome memory configured to store a syndrome result determined in a previous iteration. The decoder further includes circuitry to flip bits of the codeword based on the syndrome result and one or more parity-check equations, and a…
Who is the assignee on this patent?
Marvell Int Ltd
What technology area does this patent fall under?
Primary CPC classification H03M13/1108. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).