Memory system, memory controller and memory control method
US-9852022-B2 · Dec 26, 2017 · US
US8996962B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996962-B2 |
| Application number | US-201313848624-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 21, 2013 |
| Priority date | Aug 23, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A plurality of encrypted packets having common payload data are received, wherein each of the plurality of encrypted packets includes a corresponding parity check field, and wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error. A payload portion of each of the plurality of encrypted packets is decrypted to generate a plurality of decrypted payload portions. At least one chase coding technique is used to generate a corrected decrypted payload, based on at least one candidate bit error position and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a receiver for receiving a plurality of encrypted packets having common payload data, wherein each of the plurality of encrypted packets includes a corresponding parity check field, wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error; a processing circuit coupled to the receiver to: decrypt a payload portion of each of the plurality of encrypted packets to…
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