Fault-tolerant system and fault-tolerant operating method capable of synthesizing result by at least two calculation modules
US-9513903-B2 · Dec 6, 2016 · US
Apparatus for monitoring operating conditions of a logic circuit
US8996937B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996937-B2 |
| Application number | US-201213489034-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 5, 2012 |
| Priority date | Dec 28, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
First claim
Opening claim text (preview).
The invention claimed is: 1. An apparatus, comprising: a logic circuit configured to receive a data input signal and generate a data output signal in response to the data input signal and a transition of a clock signal; a monitor configured to receive an input signal based upon a delay of the data input signal, and configured to generate a first monitor signal in response to the input signal and the transition of the clock signal; and a determiner configured to determine from…
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- G06F11/1608Primary
Physics · mapped topic
- H03K3/0375Primary
Electricity · mapped topic
- G06F11/0751Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8996937B2 cover?
- An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signal…
- Who is the assignee on this patent?
- Jain Abhishek, Parthasarathy Chittoor, St Microelectronics Int Nv
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1608. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).