Apparatus and method to obtain information regarding suppressed faults

Patent metadata

Field	Value
Publication number	US-8996923-B2
Application number	US-201213688544-A
Country	US
Kind code	B2
Filing date	Nov 29, 2012
Priority date	Nov 29, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

First claim

What is claimed is:

1. A processor comprising:
an execution unit to execute an instruction;
a fault mask, coupled to the execution unit, to store a plurality of fault indicators, each fault indicator associated with a corresponding element of a multi-element vector, wherein a fault indicator has a first fault value when execution of the instruction by the execution unit on the corresponding element is to produce a corresponding fault, otherwise the fault indicator has a second f…

Assignees

• Intel Corp

Inventors

• Hughes Christopher J
• Corbal Jesus
• Charney Mark J
• Girkar Milind B
• Ould-Ahmed-Vall Elmoustapha
• Valentine Robert

Classifications

• G06F11/0724 Primary

  Physics · mapped topic

• G06F9/30038

  Physics · mapped topic

• G06F9/3888

  Physics · mapped topic

• G06F9/30036

  Physics · mapped topic

• G06F9/3851

  Physics · mapped topic