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Information processing apparatus with debugging unit and debugging method therefor
US8996918B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996918-B2 |
| Application number | US-201113030941-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 18, 2011 |
| Priority date | Feb 19, 2010 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.
First claim
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What is claimed is: 1. An information processing apparatus comprising: an external tool unit configured to provide a user interface for debugging; and a microcontroller that comprises: a CPU section configured to execute a program as a debugging target in a response to a first clock signal having a clock rate that is variable, wherein the clock rate of said first clock signal is changed in response to an instruction from said CPU section; a first transmitting section configur…
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Frequently asked questions
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- What does patent US8996918B2 cover?
- An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU se…
- Who is the assignee on this patent?
- Matsukawa Kazuya, Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F13/38. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).