Architecture for managing asynchronous resets in a system-on-a-chip
US-2024192745-A1 · Jun 13, 2024 · US
Server system and auto-reset method of the same
US8996850B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996850-B2 |
| Application number | US-201313798151-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Nov 30, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A server system having an auto-reset mechanism is provided. The server system comprises a power control circuit, a power processing circuit, a CPLD and a control circuit. The power control circuit generates a control signal. The power processing circuit operates according to the control signal to receive a first power and generate a second power. The CPLD receives the second power and operates accordingly and generates a power reset signal when the CPLD finishes a update process. The control circuit controls the power control circuit to stop to generate the control signal to turn off the power processing circuit to further disable the CPLD in a certain time period according to the power reset signal and controls the power control circuit to activate the power processing circuit to further activate and reset the CPLD after the certain time period.
First claim
Opening claim text (preview).
What is claimed is: 1. An auto-reset method applied to a server system, comprising: making a power control circuit of the server system operate to generate a control signal; making a power processing circuit of the server system operate according to the control signal to receive a first power source and generate a second power source; making a CPLD of the server system receive the second power source and operate accordingly; making a function circuit module of the server rec…
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- G06F1/24Primary
Physics · mapped topic
Electricity · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8996850B2 cover?
- A server system having an auto-reset mechanism is provided. The server system comprises a power control circuit, a power processing circuit, a CPLD and a control circuit. The power control circuit generates a control signal. The power processing circuit operates according to the control signal to receive a first power and generate a second power. The CPLD receives the second power and operates …
- Who is the assignee on this patent?
- Inventec Pudong Tech Corp, Inventec Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F1/24. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).