Method and system for integrity protection for accelerator device firmware using virtualization-based security
US-2024354415-A1 · Oct 24, 2024 · US
Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making
US8996848B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996848-B2 |
| Application number | US-201213345912-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 9, 2012 |
| Priority date | Apr 8, 2004 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
An integrated circuit ( 122 ) includes an on-chip boot ROM ( 132 ) holding boot code, a non-volatile security identification element ( 140 ) having non-volatile information determining a less secure type or more secure type, and a processor ( 130 ). The processor ( 130 ) is coupled to the on-chip boot ROM ( 132 ) and to the non-volatile security identification element ( 140 ) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element ( 140 ). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: security monitoring circuitry; and storage including boot code firmware including at least first and second boot code firmware portions, each of the first and second boot code firmware portions establishing a secure mode entry sequence and an exit from secure mode, the entry and exit bracketing configurations for respectively higher security and lower security in the corresponding first and second boot code firmware portio…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8996848B2 cover?
- An integrated circuit ( 122 ) includes an on-chip boot ROM ( 132 ) holding boot code, a non-volatile security identification element ( 140 ) having non-volatile information determining a less secure type or more secure type, and a processor ( 130 ). The processor ( 130 ) is coupled to the on-chip boot ROM ( 132 ) and to the non-volatile security identification element ( 140 ) to selectively exe…
- Who is the assignee on this patent?
- Brokish Charles W, Shankar Narender Madurai, Paksoy Erdal, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1009. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).