Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
US8996833B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996833-B2 |
| Application number | US-201313793045-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 11, 2013 |
| Priority date | Mar 11, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Described herein are technologies for optimizing different cache configurations of a size-configurable cache. One configuration includes a base cache portion and a removable cache portion, each with different latencies. The latency of the base cache portion is modified to correspond to the latency of the removable portion.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit, comprising: an execution unit; a size-configurable cache being communicably connected to the execution unit, the size-configurable cache comprising: a base portion; and a removable portion, wherein the size-configurable cache is configured in a first cache configuration when the removable portion is not removed and is configured in a second cache configuration when the removable portion is removed; and a latency control block…
Physics · mapped topic
Physics · mapped topic
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