Data transfer operation completion detection circuit and semiconductor memory device provided therewith

Patent metadata

Field	Value
Publication number	US-8996738-B2
Application number	US-201414279389-A
Country	US
Kind code	B2
Filing date	May 16, 2014
Priority date	Sep 20, 2005
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

First claim

What is claimed is:

1. A method for entering a power down mode in a semiconductor device, the method comprising:
initializing a first counter to a first initial state;
initializing a second counter to a second initial state;
receiving, at a first time, an enable signal having a first logic level to enable data transfer operations;
receiving a first data transfer command;
incrementing the first counter in response to the first data transfer command;
receiving, at a second…

Assignees

• Ps4 Luxco Sarl

Inventors

• Fujisawa Hiroki

Classifications

• G11C7/1027 Primary

  Physics · mapped topic

• G11C7/1072

  Physics · mapped topic

• G11C7/20

  Physics · mapped topic

• G11C7/22

  Physics · mapped topic

• G11C11/4072

  Physics · mapped topic