Method and apparatus for receiving burst data without using external detection signal

US8995595B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8995595-B2
Application numberUS-201314132721-A
CountryUS
Kind codeB2
Filing dateDec 18, 2013
Priority dateJul 1, 2009
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for receiving a burst data signal having data edges and corresponding to burst data including an initial portion, the apparatus comprising: an input circuit configured to receive an electrical signal and output an input signal; a reference data signal generator configured to generate a reference data signal having reference edges; a clock data recovery (CDR) circuit configured to generate a clock signal having clock edges, the CDR circuit ha…

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What does patent US8995595B2 cover?
Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference …
Who is the assignee on this patent?
Megachips Corp
What technology area does this patent fall under?
Primary CPC classification H04L7/0075. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).