IC processor reconstucting two consecutive lost packets from secondary information

US8995430B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8995430-B2
Application numberUS-201313859909-A
CountryUS
Kind codeB2
Filing dateApr 10, 2013
Priority dateApr 2, 1996
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet transmissions and holds bits defining reconstruction of a packet stream having a primary stage and a secondary stage. The secondary stage has one or more of linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains. The packet stream has an instance of single packet loss, and the reconstruction includes receiving a packet sequence represented by P(n)P(n−1)′, [Lost Packet], P(n+2)P(n+1)′, and P(n+3)P(n+2)′, obtaining as information from the secondary stage one or more of the linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains, and performing an excitation reconstruction utilizing said packet sequence thus received.

First claim

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What is claimed is: 1. A single-chip integrated circuit comprising: A. a processor circuit; and B. a memory on said single-chip integrated circuit holding bits defining reconstruction of a stream of packets with each packet having a primary stage and a secondary stage, the secondary stage having one or more of LPC parameters, LTP lags, parity check, and adaptive and fixed codebook gains of the first stage of a preceding packet, and the reconstruction including: i. receiving a p…

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What does patent US8995430B2 cover?
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet transmissions and holds bits defining reconstruction of a packet stream having a primary stage and a secondary stage. The secondary s…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H04L47/34. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).