Solid state imaging device having a plurality of unit cells

US8994863B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994863-B2
Application numberUS-68549310-A
CountryUS
Kind codeB2
Filing dateJan 11, 2010
Priority dateNov 20, 2002
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell ( 30 ) includes two pixels ( 31 ) and ( 32 ). Upper and lower photoelectric converters ( 33 ) and ( 34 ), transfer transistors ( 35 ) and ( 36 ) connected to the upper and lower photoelectric converters, respectively, a reset transistor ( 37 ), and an amplifying transistor ( 38 ) form the two pixels ( 31 ) and ( 32 ). A full-face signal line 39 is connected to the respective drains of the reset transistor ( 37 ) and the amplifying transistor ( 38 ). Controlling the full-face signal line ( 39 ), along with transfer signal lines ( 42 ) and ( 43 ) and a reset signal line ( 41 ), to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

First claim

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What is claimed is: 1. A solid-state imaging device comprising: an imaging area having a plurality of unit cells arranged in a two-dimensional array, each unit cell including: a plurality of pixels; a plurality of photoelectric converters, each photoelectric converter of the plurality of photoelectric converters corresponding to one of the plurality of pixels; an amplifying transistor, shared by at least two pixels of the plurality of pixels, that amplifies a signal read out…

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What does patent US8994863B2 cover?
A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell ( 30 ) includes two pixels ( 31 ) and ( 32 ). Upper and lower photoelectric converters ( 33 ) and ( 34 ), transfer transistors ( 35 ) and ( 36 ) connected…
Who is the assignee on this patent?
Abe Takashi, Nakamura Nobuo, Umeda Tomoyuki, and 5 more
What technology area does this patent fall under?
Primary CPC classification H04N25/766. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).