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US-2024311371-A1 · Sep 19, 2024 · US
Cache line allocation method and system
US8994740B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994740-B2 |
| Application number | US-201213448255-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 16, 2012 |
| Priority date | Apr 19, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number.
First claim
Opening claim text (preview).
What is claimed is: 1. A cache line allocation method, wherein a cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/0875Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8994740B2 cover?
- A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first numb…
- Who is the assignee on this patent?
- Gao Bingxu, Chen Xian, Via Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0875. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).