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Latch circuit and display device using the latch circuit
US8994704B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994704-B2 |
| Application number | US-201213429476-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 26, 2012 |
| Priority date | May 12, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A latch circuit includes an input transistor, a retention capacitor connected between an electrode of the input transistor and a first latch control line, a first transistor having an electrode connected to the first latch control line and a gate connected to the electrode of the input transistor, a second transistor having a gate connected to another electrode of the first transistor and an electrode is connected to the second latch control line, a third transistor having a gate connected to the another electrode of the first transistor and an electrode connected to another electrode of the second transistor and another electrode connected to an output terminal.
First claim
Opening claim text (preview).
What is claimed is: 1. A latch circuit for receiving and latching data in response to an input scanning signal comprising: a first latch control line receiving a first drive clock; a second latch control line receiving a second drive clock; an input transistor having a gate and first and second electrodes, the first electrode of the input transistor receiving a data signal corresponding to 0 data or 1 data in response to the scanning signal supplied to the gate of the input transis…
Assignees
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Classifications
- H03K3/356095Primary
Electricity · mapped topic
- G09G3/20Primary
Physics · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994704B2 cover?
- A latch circuit includes an input transistor, a retention capacitor connected between an electrode of the input transistor and a first latch control line, a first transistor having an electrode connected to the first latch control line and a gate connected to the electrode of the input transistor, a second transistor having a gate connected to another electrode of the first transistor and an el…
- Who is the assignee on this patent?
- Miyazawa Toshio, Miyamoto Mitsuhide, Pixtronix Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K3/356095. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).