Display device and electronic device having plural gate drivers

Patent metadata

Field	Value
Publication number	US-8994636-B2
Application number	US-79493910-A
Country	US
Kind code	B2
Filing date	Jun 7, 2010
Priority date	Jun 25, 2009
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

First claim

The invention claimed is:

1. A display device comprising:
a plurality of gate lines provided so as to be parallel or substantially parallel;
a first gate driver electrically connected to each of odd-numbered gate lines of the plurality of gate lines; and
a second gate driver electrically connected to each of even-numbered gate lines of the plurality of gate lines,
wherein the first gate driver includes a k-th flip flop circuit and a k-th transfer signal generation circuit,…

Assignees

• Umezaki Atsushi
• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• G09G2300/0426

  Physics · mapped topic

• H03K17/04

  Electricity · mapped topic

• G09G2310/0267

  Physics · mapped topic

• G09G3/3677

  Physics · mapped topic

• G09G3/3648 Primary

  Physics · mapped topic