Gate shift register and display device comprising the same

US8994629B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994629-B2
Application numberUS-201213710043-A
CountryUS
Kind codeB2
Filing dateDec 10, 2012
Priority dateSep 27, 2012
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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According to an embodiment, a gate shift register includes a plurality of stages cascade-connected to each other. An nth one of the stages includes: a pull-up transistor that outputs any one of gate shift clocks as an nth scan pulse of a gate high voltage in accordance with the potential of a Q node; a pull-down transistor that is connected to the pull-up transistor through an output node, and outputs a low-potential voltage as an nth scan pulse of a gate low voltage in accordance with the potential of a QB node; and a switching circuit that charges and discharges the Q node and the QB node, respectively, or vice versa in response to a set signal and a reset signal, wherein an adaptively adjusted variable high-potential voltage is applied to the QB node to correspond to a shift in the threshold voltage of the pull-down transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising a gate shift register, the display device comprising: a display panel; a gate shift register comprising a plurality of stages cascade-connected to each other and sequentially supplying scan pulses to scan lines of the display panel; a threshold voltage sensing circuit comprising a monitoring TFT and a detection TFT and outing a sensed voltage; and a VDD regulator circuit that calculates a threshold voltage of a pull-down tra…

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What does patent US8994629B2 cover?
According to an embodiment, a gate shift register includes a plurality of stages cascade-connected to each other. An nth one of the stages includes: a pull-up transistor that outputs any one of gate shift clocks as an nth scan pulse of a gate high voltage in accordance with the potential of a Q node; a pull-down transistor that is connected to the pull-up transistor through an output node, and …
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3266. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).