Signal distortion correction with time-to-digital converter (tdc)
US-2024348417-A1 · Oct 17, 2024 · US
US8994575B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994575-B2 |
| Application number | US-201313759383-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 5, 2013 |
| Priority date | Aug 6, 2010 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.
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What is claimed is: 1. An analog-to-digital (AD) converter comprising: a time detection circuit; a reference signal generation unit configured to generate a reference signal; and a calculation unit configured to generate a digital signal based on logic states latched in a latch unit and a state latched by a count latch unit, wherein the time detection circuit comprises: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input sig…
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