Time detection circuit, ad converter, and solid state image pickup device

US8994575B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994575-B2
Application numberUS-201313759383-A
CountryUS
Kind codeB2
Filing dateFeb 5, 2013
Priority dateAug 6, 2010
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.

First claim

Opening claim text (preview).

What is claimed is: 1. An analog-to-digital (AD) converter comprising: a time detection circuit; a reference signal generation unit configured to generate a reference signal; and a calculation unit configured to generate a digital signal based on logic states latched in a latch unit and a state latched by a count latch unit, wherein the time detection circuit comprises: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input sig…

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What does patent US8994575B2 cover?
A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of t…
Who is the assignee on this patent?
Olympus Corp
What technology area does this patent fall under?
Primary CPC classification G04F10/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).