Fractional divider using a calibrated digital-to-time converter
US-2017364034-A1 · Dec 21, 2017 · US
Digital-to-time converter and calibration of digital-to-time converter
US8994573B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994573-B2 |
| Application number | US-201313833256-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 15, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC.
First claim
Opening claim text (preview).
What is claimed is: 1. A digital-to-time converter comprising a gate controller configured to receive at least a portion of a first digital value and at least a portion of a second digital value, the first digital value and the second digital value to be converted to time instants of a rising edge and a falling edge of an output signal of the digital-to-time converter, and further configured to generate a gate enable signal based on at least the portions of the first and second di…
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- H03M1/82Primary
Electricity · mapped topic
Physics · mapped topic
Electricity · mapped topic
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- What does patent US8994573B2 cover?
- A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable sig…
- Who is the assignee on this patent?
- Intel Mobile Comm Gmbh
- What technology area does this patent fall under?
- Primary CPC classification H03M1/82. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).