Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US8994439B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994439-B2 |
| Application number | US-201313862932-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 15, 2013 |
| Priority date | Apr 19, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first circuit comprising a first transistor; and a second circuit electrically connected to a gate of the first transistor through a first signal line, the second circuit comprising: first to n-th inverters being sequentially connected in series, wherein n is a natural number larger than one; a bootstrap circuit; and a delay circuit, wherein an input terminal of the first inverter is electrically connected to a…
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