Coincident tracking turn-on for mixed voltage logic

Patent metadata

Field	Value
Publication number	US-8994434-B2
Application number	US-201313765094-A
Country	US
Kind code	B2
Filing date	Feb 12, 2013
Priority date	Feb 13, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power.

First claim

What is claimed is:

1. A method of dealing high inrush current on applying voltage to a mixed voltage logic integrated circuits comprising:
adding only a single Field Effect Transistor to a linear voltage regulator of said mixed voltage logic integrated circuits, wherein the single Field Effect Transistor and the linear voltage regulator operate only on a single supply power; and
ramping up core voltage coincidentally with Input/Output voltage until a threshold of said linear vo…

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Willis Scott C
• Singleton William C
• Buchanan Russell

Classifications

• H03K17/08104 Primary

  Electricity · mapped topic