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Flip-flop circuit having set/reset circuit
US8994431B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994431-B2 |
| Application number | US-201313925815-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 24, 2013 |
| Priority date | Jun 28, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
A flip-flop circuit includes an input stage circuit, a middle stage circuit, an output stage circuit and a set/reset circuit. The input stage circuit is arranged for receiving a first signal from a first node, and selectively outputting a second signal at a second node according to at least one control signal. The middle stage circuit is coupled to the input stage circuit, and arranged for receiving the second signal, and selectively outputting a third signal at a third node according to the at least one control signal. The output stage circuit is coupled to the middle stage circuit, and arranged for receiving the third signal to output an output signal. The set/reset circuit is coupled to the second node and the third node, and arranged to receiving a set signal and a reset signal, and selectively determining a voltage level of the third signal at the third node.
First claim
Opening claim text (preview).
What is claimed is: 1. A flip-flop circuit, comprising: an input stage circuit, arranged for receiving a first signal from a first node, and selectively outputting a second signal corresponding to the first signal at a second node according to at least one control signal; a middle stage circuit, coupled to the input stage circuit, arranged for receiving the second signal, and selectively outputting a third signal corresponding to the second signal at a third node according to th…
Assignees
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Classifications
- H03K3/013Primary
Electricity · mapped topic
- H03K3/356191Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994431B2 cover?
- A flip-flop circuit includes an input stage circuit, a middle stage circuit, an output stage circuit and a set/reset circuit. The input stage circuit is arranged for receiving a first signal from a first node, and selectively outputting a second signal at a second node according to at least one control signal. The middle stage circuit is coupled to the input stage circuit, and arranged for rece…
- Who is the assignee on this patent?
- Silicon Motion Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K3/013. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).