Oscillator circuits and methods to compensate frequency pulling
US-2015381186-A1 · Dec 31, 2015 · US
Use of Frequency addition in a PLL control loop
US8994422B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994422-B2 |
| Application number | US-201314055772-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 16, 2013 |
| Priority date | Oct 17, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.
First claim
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What is claimed is: 1. A phase-locked loop for locking a phase of an output signal to a reference signal, the output signal having a frequency that is different from a frequency of the reference signal, comprising: an oscillator configured to generate a plurality of analog signals at a selected frequency, each of the plurality of analog signals having a different phase such that the phases of the plurality of analog signals are distributed equally across a cycle of the frequency o…
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- What does patent US8994422B2 cover?
- A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offs…
- Who is the assignee on this patent?
- Ess Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H03L7/18. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).