Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizers
US-2024171181-A1 · May 23, 2024 · US
US8994419B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994419-B2 |
| Application number | US-201314109667-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2013 |
| Priority date | Aug 19, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: first to fourth output lines; an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively; a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth i…
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.