Semiconductor device, semiconductor system including the same, and method for operating the same

US8994419B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994419-B2
Application numberUS-201314109667-A
CountryUS
Kind codeB2
Filing dateDec 17, 2013
Priority dateAug 19, 2013
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: first to fourth output lines; an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively; a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth i…

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What does patent US8994419B2 cover?
A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H03K5/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).