Method and arrangement for generating a clock signal by means of a phase locked loop

US8994418B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994418-B2
Application numberUS-201414189410-A
CountryUS
Kind codeB2
Filing dateFeb 25, 2014
Priority dateFeb 27, 2013
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for generating a clock signal by a phase locked loop, in which a divided clock signal generated from the clock signal is compared with a reference clock, and a frequency and a phase angle of the clock signal to be generated is set as a function of said comparison, comprising: generating a plurality of delayed divided clock signals respectively shifted by a time difference delta t from the divided clock signal, generating a capture signal under…

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Classifications

  • H03L7/08Primary

    Electricity · mapped topic

  • H03L7/091Primary

    Electricity · mapped topic

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What does patent US8994418B2 cover?
A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an e…
Who is the assignee on this patent?
Univ Dresden Tech
What technology area does this patent fall under?
Primary CPC classification H03L7/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).