Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
US8994418B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994418-B2 |
| Application number | US-201414189410-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2014 |
| Priority date | Feb 27, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.
Opening claim text (preview).
The invention claimed is: 1. A method for generating a clock signal by a phase locked loop, in which a divided clock signal generated from the clock signal is compared with a reference clock, and a frequency and a phase angle of the clock signal to be generated is set as a function of said comparison, comprising: generating a plurality of delayed divided clock signals respectively shifted by a time difference delta t from the divided clock signal, generating a capture signal under…
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.