Semiconductor Integrated Circuit and Semiconductor Device
US-2024162894-A1 · May 16, 2024 · US
Adaptive multi-stage slack borrowing for high performance error resilient computing
US8994416B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994416-B2 |
| Application number | US-201314045642-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 3, 2013 |
| Priority date | Jan 7, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
First claim
Opening claim text (preview).
The invention claimed is: 1. A circuit comprising: a flip-flop having a D input for receiving input data, a set input, a reset input, and a Q output; a transition detector having an output configured to detect a transition in the input data within a time window; a first multiplexer having a first input for receiving a global set signal, a second input for receiving the input data, a control input coupled to the output of the transition detector, and an output coupled to the se…
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- H03K3/0375Primary
Electricity · mapped topic
- H03K3/02Primary
Electricity · mapped topic
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- What does patent US8994416B2 cover?
- Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dy…
- Who is the assignee on this patent?
- St Microelectronics Int Nv, St Microelectronics Sa
- What technology area does this patent fall under?
- Primary CPC classification H03K3/0375. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).