Semiconductor device with buffer and replica circuits

Patent metadata

Field	Value
Publication number	US-8994401-B2
Application number	US-201314018784-A
Country	US
Kind code	B2
Filing date	Sep 5, 2013
Priority date	Dec 17, 2009
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an input buffer comprising:
first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer; and
first and second NMOS transistors serially interconnected between a second power supply node and the output node of the input buffer,
wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input node of the i…

Assignees

• Elpida Memory Inc
• Ps4 Luxco Sarl

Inventors

• Hatakeyama Toru
• Ishikawa Toru

Classifications

• H03K19/0027 Primary

  Electricity · mapped topic

• G11C7/1087

  Physics · mapped topic

• G11C5/06

  Physics · mapped topic