Semiconductor device package and methods for producing same

Patent metadata

Field	Value
Publication number	US-8994161-B2
Application number	US-61910607-A
Country	US
Kind code	B2
Filing date	Jan 2, 2007
Priority date	Jan 3, 2006
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.

First claim

The invention claimed is:

1. An apparatus, comprising:
a semiconductor chip supported on a chip island;
a filler layer encapsulating the semiconductor chip;
a heat sink;
through contacts extending, through the filler layer to an upper surface of the filler layer, the through contacts separated from the heat sink by a first trench cut into the upper surface of the filler layer, the through contacts being separated by a second trench from a vertical wall of the filler layer adjacent to the upper surface of the filler layer, the through contacts lying between the first trench and the second trench, the through contacts having exposed areas positioned along an outer edge of the first and second trenches, the exposed areas separated from each other by regions of the filler layer, wherein the heat sink terminates flush with an inner edge of the first trench and the first trench contains an electrically insulating material; and
contact bumps, partially embedded within the filler layer and connected to an upper surface of the semiconductor chip by bonding wires, wherein the chip island, the through contacts, and the contact bumps terminate flush with a lower surface of the filler layer.

2. The apparatus of claim 1 , wherein the heat sink has regions having different thickness.

3. The apparatus of claim 2 , wherein the heat sink is positioned above the semiconductor chip.

4. The apparatus of claim 3 , wherein the heat sink has a thicker region adjacent an upper surface of the semiconductor chip and a thinner region positioned above the bonding wires to provide clearance for the bonding wires.

5. The apparatus of claim 1 , wherein the filler layer covers a top and sides of the semiconductor chip.

6. The apparatus of claim 1 , wherein the heat sink has a thicker region adjacent to an upper surface of the semiconductor chip to reduce the distance between the semiconductor chip and the heat sink.

7. The apparatus of claim 1 , wherein the exposed areas of the through contacts form contact pads.

8. The apparatus of claim 1 , wherein the at least one trench comprises two trenches, wherein the heats sink lies substantially centrally between the two trenches and terminates flush with the inner edges of the two trenches.

9. An apparatus, comprising:
a semiconductor chip supported by a chip island;
a filler layer encapsulating a top and sides of the semiconductor chip;
a heat sink thermally coupled to and separated from the semiconductor chip by a portion of the filler layer, wherein a portion of the heat sink is thicker proximate to the semiconductor chip;
through contacts extending, through the filler layer to an upper surface of the filler layer, the through contacts separated from the heat sink by a first trench cut into the upper surface of the filler layer, the through contacts being separated by a second trench from a vertical wall of the filler layer adjacent to the upper surface of the filler layer, the through contacts lying between the first trench and the second trench, the through contacts having exposed areas positioned along an outer edge of the first and second trenches, the exposed areas separated from each other by regions of the filler layer, wherein the heat sink terminates flush with an inner edge of the first trench and the first trench contains an electrically insulating material;
contact bumps, partially embedded within the filler layer and connected to an upper surface of the semiconductor chip by bonding wires; and
bonding wires electrically connected between the top of the semiconductor chip and the contact bumps, wherein the chip island, the through contacts, and the contact bumps terminate flush with a lower surface of the filler layer.

10. Apparatus, comprising:
a semiconductor chip supported on a chip island;
a filler layer encapsulating the semiconductor chip;
a heat sink;
through contacts extending upwardly nearly to an upper surface of the filler layer, the through contacts being separated from the heat sink by a first trench cut into the upper surface of the filler layer, the through contacts being separated by a second trench from a vertical wall of the filler layer adjacent to the upper surface of the filler layer, and the through contacts lying between the first trench and the second trench; and
contact bumps, partially embedded within the filler layer and connected to an upper surface of the semiconductor chip by bonding wires, wherein the chip island, the through contacts, and the contact bumps terminate flush with a lower surface of the filler layer.

Assignees

• Ahr Michael
• Lanchava Bakuri
• Infineon Technologies Ag

Inventors

• Ahr Michael
• Lanchava Bakuri

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title