Semiconductor integrated circuit with TSV bumps

Patent metadata

Field	Value
Publication number	US-8994110-B2
Application number	US-201314088466-A
Country	US
Kind code	B2
Filing date	Nov 25, 2013
Priority date	Nov 28, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.

First claim

What is claimed is:

1. A semiconductor integrated circuit, comprising:
a plurality of through silicon via (TSV) bumps;
a plurality of input/output (I/O) buffers connected to said plurality of TSV bumps, respectively; and
first and second main power lines,
wherein said plurality of I/O buffers respectively include a plurality of electrostatic discharge (ESD) protection circuitries,
wherein each of said ESD protection circuitries includes:
a P-channel ESD protection circui…

Assignees

• Renesas Electronics Corp

Inventors

• Ishikawa Kenichi

Classifications

• H10W90/722

  Electricity · mapped topic

• H10W90/00

  Electricity · mapped topic

• H10W72/248

  Electricity · mapped topic

• H10W72/244

  Electricity · mapped topic

• H10W72/232

  Electricity · mapped topic