Gate isolation features and methods of fabricating the same in semiconductor devices
US-2024379673-A1 · Nov 14, 2024 · US
US8994098B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994098-B2 |
| Application number | US-201313938446-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 10, 2013 |
| Priority date | Jul 12, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first pillar transistor including a first diffusion layer on an upper portion of a first silicon pillar formed on a substrate, a second diffusion layer on a lower portion of the first silicon pillar, and a first gate electrode formed via a first gate insulator film so as to cover a surface of the first silicon pillar between the first diffusion layer and the second diffusion layer; a second pillar transistor including a…
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