Semiconductor memory device with a buried drain and its memory array

US8994095B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994095-B2
Application numberUS-201013322640-A
CountryUS
Kind codeB2
Filing dateDec 24, 2010
Priority dateDec 24, 2009
Publication dateMar 31, 2015
Grant dateMar 31, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate ( 107 ); one drain region ( 108 ) of a first doping type; two source regions ( 101 a, 101 b ) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

First claim

Opening claim text (preview).

What is claimed: 1. A semiconductor memory device with a buried drain, comprising: a semiconductor substrate ( 107 ), a drain of a first conductivity ( 108 ), two sources of a second conductivity ( 101 a , 101 b ), and a gate stack with charge trapping layer to locally trap electrons, the gate stack having: a first dielectric layer ( 104 ) with a width of bandgap covering the channel region ( 106 ), a second dielectric layer ( 103 ) disposed over the said first diel…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8994095B2 cover?
A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate ( 107 ); one drain region ( 108 ) of a first doping type; two source regions ( 101 a, 101 b ) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a ma…
Who is the assignee on this patent?
Wang Pengfei, Sun Qingqing, Ding Shijin, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10D64/035. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).