Field-effect transistor (FET) with self-aligned ferroelectric capacitor and methods of fabrication
US-12166122-B2 · Dec 10, 2024 · US
US8994095B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994095-B2 |
| Application number | US-201013322640-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 24, 2010 |
| Priority date | Dec 24, 2009 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate ( 107 ); one drain region ( 108 ) of a first doping type; two source regions ( 101 a, 101 b ) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.
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What is claimed: 1. A semiconductor memory device with a buried drain, comprising: a semiconductor substrate ( 107 ), a drain of a first conductivity ( 108 ), two sources of a second conductivity ( 101 a , 101 b ), and a gate stack with charge trapping layer to locally trap electrons, the gate stack having: a first dielectric layer ( 104 ) with a width of bandgap covering the channel region ( 106 ), a second dielectric layer ( 103 ) disposed over the said first diel…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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