Semiconductor device with enhanced discrimination between selected and non-selected memory cells

Patent metadata

Field	Value
Publication number	US-8994092-B2
Application number	US-201314103829-A
Country	US
Kind code	B2
Filing date	Dec 11, 2013
Priority date	Dec 19, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, −7 V is applied to the drain of a selected nonvolatile memory cell, −8 V is applied to the gate electrode of the selection transistor, and further −3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.

First claim

What is claimed is:

1. A semiconductor device comprising a first nonvolatile memory cell formed on a semiconductor substrate having a first conductivity type,
the first nonvolatile memory cell including:
(a) a first well which is formed on a major surface of the semiconductor substrate and has a second conductivity type different from the first conductivity type, and a first active region formed in the first well;
(b) a second well which is formed on the major surface of the s…

Assignees

• Renesas Electronics Corp

Inventors

• Yamakoshi Hideaki

Classifications

• G11C16/00

  Physics · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• G11C16/0408 Primary

  Physics · mapped topic

• H10B41/35 Primary

  Electricity · mapped topic