Memory device made from stacked substrates bonded with a resin containing conductive particles

US8994086B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994086-B2
Application numberUS-90431310-A
CountryUS
Kind codeB2
Filing dateOct 14, 2010
Priority dateNov 11, 2004
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first element forming layer; a second element forming layer adhered to the first element forming layer by an adhesive layer made of conductive particles dispersed in a resin, wherein the first element forming layer includes: a first transistor and a second transistor; an interlayer insulating layer which covers the first transistor and the second transistor; a first conductive layer functioning as an antenna over…

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What does patent US8994086B2 cover?
The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which fun…
Who is the assignee on this patent?
Yamazaki Shunpei, Abe Hiroko, Nemoto Yukie, and 3 more
What technology area does this patent fall under?
Primary CPC classification H10D84/038. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).