Gate isolation features and methods of fabricating the same in semiconductor devices
US-2024379673-A1 · Nov 14, 2024 · US
Stacked carbon-based FETs
US8994080B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994080-B2 |
| Application number | US-201313968101-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 15, 2013 |
| Priority date | May 9, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.
First claim
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What is claimed is: 1. A stacked transistor device, comprising: a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed directly over the lower channel layer, said pair of source regions being separated by an insulator; a pair of vertically aligned drain regions formed directly over the lower channel layer, said pair of drain regions being separated by an insulator; conductive source and drain extensions, each formed in the substrate i…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994080B2 cover?
- Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned ga…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D84/83. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).