Vertical JFET with body diode and device regions disposed in a single compound epitaxial layer
US-9209318-B2 · Dec 8, 2015 · US
Semiconductor device
US8994078B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994078-B2 |
| Application number | US-201213537180-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 29, 2012 |
| Priority date | Jun 29, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a cell region and a contact region, the cell region comprising a functional unit including a gate electrode, a source and a drain electrode, the contact region comprising a gate pad, wherein the gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, wherein the gate electrode and the gate pad are laterally separated from one another and are arranged on mesa p…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994078B2 cover?
- A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main su…
- Who is the assignee on this patent?
- Kueck Daniel, Elpelt Rudolf, Infineon Technologies Austria
- What technology area does this patent fall under?
- Primary CPC classification H10D30/831. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).