Hydrogen mitigation schemes in the passivation of advanced devices

US8994073B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994073-B2
Application numberUS-201213644506-A
CountryUS
Kind codeB2
Filing dateOct 4, 2012
Priority dateOct 4, 2012
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).

First claim

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What is claimed is: 1. A semiconductor device comprising: a semiconductor body; and a passivation structure on a surface of the semiconductor body, the passivation structure comprising: one or more Hydrogen-free Silicon Nitride layers on the surface of the semiconductor body; a Hydrogen barrier layer having more than one oxide layer on a surface of the one or more Hydrogen-free Silicon Nitride layers opposite the semiconductor body; and an additional Silicon Nitride layer o…

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What does patent US8994073B2 cover?
Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semicondu…
Who is the assignee on this patent?
Cree Inc
What technology area does this patent fall under?
Primary CPC classification H10D30/4755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).