Power mosfet and manufacturing method thereof
US-2024322032-A1 · Sep 26, 2024 · US
US8994066B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994066-B2 |
| Application number | US-201414516598-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 17, 2014 |
| Priority date | Jun 8, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a semiconductor layer having a plurality of impurity regions forming a transistor; a gate trench formed in the semiconductor layer; a gate electrode buried in the gate trench and having an upper surface flush with a front surface of the semiconductor layer; a diode trench formed in the semiconductor layer; and a double-ended zener diode buried in the diode trench and having an upper surface flush with the front sur…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.