Manufacturing method of semiconductor device

US8994066B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994066-B2
Application numberUS-201414516598-A
CountryUS
Kind codeB2
Filing dateOct 17, 2014
Priority dateJun 8, 2011
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a semiconductor layer having a plurality of impurity regions forming a transistor; a gate trench formed in the semiconductor layer; a gate electrode buried in the gate trench and having an upper surface flush with a front surface of the semiconductor layer; a diode trench formed in the semiconductor layer; and a double-ended zener diode buried in the diode trench and having an upper surface flush with the front sur…

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What does patent US8994066B2 cover?
A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench form…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/668. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).