Structure, structure and method of latch-up immunity for high and low voltage integrated circuits

US8994026B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994026-B2
Application numberUS-201313774205-A
CountryUS
Kind codeB2
Filing dateFeb 22, 2013
Priority dateJul 31, 2008
Publication dateMar 31, 2015
Grant dateMar 31, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.

First claim

Opening claim text (preview).

What is claimed is: 1. A structure comprising a first dopant type structure embedded in a diffused deep structure formed of a same dopant type of the first dopant type structure, the first dopant type structure being a retrograde N-well and the diffused deep structure being a diffused N-Tub structure, the diffused deep structure being associated with a non-isolated CMOS logic, the diffused deep structure being embedded in a P-wafer and provided below the first dopant type structure…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8994026B2 cover?
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D84/0191. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).